The present invention relates to a logic semiconductor device combined with a nonvolatile semiconductor memory and a method for fabricating the same; a semiconductor device group including a semiconductor device with no nonvolatile semiconductor memory and a semiconductor device combined with a nonvolatile semiconductor memory and a method for fabricating the same; and the semiconductor devices included by the semiconductor device group.
The logic semiconductor device combined with a nonvolatile semiconductor memory forms product fields, as of CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array), and because of their characteristic of programmability, so far have formed large markets because of their characteristic, programmability.
FPGA is basically formed of reconfigurable interconnections based on SRAM, etc. laid on a chip. Specific reconfigurable program data are stored in a flash memory (Flash EPROM), etc. which are formed on other chips, etc. Every time the source power is turned on, the data stored in the flash memory are transmitted to the FPGA chip for programming. This structure causes problems that the startup is slow upon the turn-on of the source power and that the program data can be read at the outside unpreferably for the security, and other problems.
In order to solve these problems, the FPGA chip combined with a flash memory, which can store program data is being developed. The steps of fabricating the FPGA chip combined with a flash memory are increased by a number of the steps of forming the flash memory in comparison with the steps of fabricating the usual FPGA chip. This causes a new problem of the fabrication cost increase.
In such background, the FPGA which requires high security will use a chip combined with a flash memory, and for the price of the chips rather than the security, the FPGA will use a chip of the logic circuits alone. Both FPGAs are different from each other in the chip structure but are basically the same in the function. Both are designed by using the same design macro. Efforts are made to make the characteristics of the transistors fabricated by the fabrication process combined with a flash memory and the characteristics of the transistors fabricated by the fabrication process combined with no flash memory as close as possible.
Reference 1 (Japanese published unexamined patent application No. 2001-196470) discloses a fabrication process in which wells, etc. for the transistors forming the main logic circuit are formed after the wells for forming the flash memory cells, the wells for the high-voltage transistors, the floating gates of the flash memory cells, etc. have been formed. The specific fabrication process of the flash memory is thus performed before the process for fabricating the transistors forming the logic circuit is performed, whereby the channel impurity distribution of the transistors forming the logic circuit can be made substantially the same as that of the logic circuit combined with no flash memory.
In the logic semiconductor device combined with a nonvolatile memory, in addition to a flash memory, high-voltage transistors for controlling the flash memory and low-voltage transistors of the high-performance logic circuit are integrated on one semiconductor chip. To this end, a plurality of kinds of gate insulating films having different thicknesses must be formed. A method for forming a plurality of kinds of gate insulating films of different thicknesses is described in, Reference 1, Reference 2 (Japanese published unexamined patent application No. Hei 11-317458), Reference 3 (Japanese published unexamined patent application No. Hei 10-199994), Reference 4 (Japanese published unexamined patent application No. 2002-368145), Reference 5 (Japanese published unexamined patent application No. 2000-315733), and Reference 6 (Japanese published unexamined patent application No. 2003-007863).
In the method described in Reference 2, a thick gate insulating film is grown on the entire surface, the thick insulating film in a region where a thin gate insulating film is to be formed is removed by photolithography, and the thin gate insulating film is grown.
The methods described in References 1, 3 and 4 each use the method described in Reference 2, and the step of removing the part of the thick gate insulating film and the step of forming wells are performed by using one mask, whereby the fabrication step number is decreased.